My client is a leading tech-driven prop trading firm, trading their own capital across a broad range of asset classes, instruments and strategies in markets worldwide. They are looking for exceptional verification engineers to join a highly talented team where you'll design and build a cutting-edge, low-latency trading application.
Within this smart group of polyglots and technologists, developers here have large amounts of autonomy and are always looking for the very best tool to solve each individual problem. Here there is very little red tape, and a rapid feedback loop on the software you build. They are firm believers in automated testing and lightly-coupled architectures.
You will collaborate with other engineers, traders, and researchers to expand the platform's capabilities across all aspects of individual block-level and full project level verification. This will include framework/environment development, test plan development and execution, code/functional coverage closure and reviews. Requirements:
- 2+ years' experience relevant experience in ASIC/FPGA Verification
- Strong coding skills in SystemVerilog and Python
- Deep Python knowledge, especially for high level stimulus generation and model coverage
- Previous exposure to functional coverage and code coverage
- Desirable: C/C++, DPI interface to simulators, or hardware integration testing experience
- Candidates must be based in the USA and have a valid working visa (H1B/Green Card)
- Top of the market compensation package
- Culture has the lively spirit of a start-up, with stability of a longer-established firm
- Feel valued for your input and get rewarded for great ideas
Remote interviews are available if required. Contact
If you feel you are a good match, please don't hesitate to get in touch with: George James